Faculty Profile

Mr. Noble G
Assistant Professor

Mr. Noble G completed M. Tech in VLSI Design from VIT University in the year 2014. He completed his B.Tech in Electronics and Communication Engineering from Viswajyothi College of Engineering And Technology, Vazhakulam in the year 2012. He joined as Asst.Professor in FISAT on 7th August  2014.

  1. “MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles”, 36th International Conference on VLSI Design & 22nd International Conference on Embedded Systems (VLSID 2023), January 2023.
  2. “Accelerators for Sparse Matrix-Matrix Multiplication: A Review”, IEEE 19th India Council International Conference (INDICON), November 2022.
  3. Implementation and Analysis of an Evolutionary Optimized Non-Linear Function for Linearization of Thermo-Resistive Sensors. International Conference on Devices, Circuits and Systems (ICDCS), April 2022 · Apr 30, 2022
  4. Synthesis and study of evolutionarily optimized sensor linearisation with translinear & FPGA circuits. International Journal of Electronics, Taylor& Francis, DOI: 10.1080/00207217.2021.1941287 · Jul 26, 2021
  5. Implementation of Pipelined Out Of Order Queue Processor Architecture. International Journal of Research in Engineering and Applied Science (ISSN 2249-3905), Volume 5, Issue 9 · Sep 30, 2015
  6. Direct Digital Frequency Synthesizer Based On CORDIC Algorithm. International journal of Innovative Research in Computer and Communication Engineering (ISSN (Online): 2320-9801, ISSN (Print): 2320-9798), Volume 3, Issue 8, August 2015 · Aug 1, 2015
  7. Novel Flip-Flop Design for Low Power Clocking System. IEEE International Conference on Communication and Signal Processing (ICCSP13) · Apr 3, 2013

Winner of the IDEATe competition conducted by the Kerala Start-up Mission in 2023.

Recipient of the VLSID-2023 Fellowship.

Mentored 4 teams in Smart India Hackaton Grand Finale 2022

Kerala Startup Mission Innovators Grant
Project Title: Smart Soldering Iron
Sanctioned Year: 2022

CERD Project Grant by APJ Abul Kalam Technological University, Kerala
Project Title: Fast walkthrough gateway
Sanctioned Year: 2021

Project grant from Kerala State Council for Science and Technology [KSCSTE]
Project Title: Face Mask Detection System
Sanctioned Year: 2021

Project grant from Kerala State Council for Science and Technology [KSCSTE]
Project Title: Bore well Rescue Robot
Sanctioned Year: 2019


IoT based chair/cot usage detector
Published on May 7, 2021

Smart Soldering Iron
Filed Jun 14, 2021

M.Tech First rank in VLSI Design from Vellore Institute of Technology [VIT University]

Resource person for the following programmes

  • Workshop on Free Simulation Software’s and PCB Design : January 2015
  • Workshop on VLSI Design flow and Chip design: July 2015
  • Evening workshop on embedded system design : August 2015
  • Workshop on PIC microcontroller and PCB design : January 2016
  • Workshop on Arduino board and robotics : December 2016
  • Workshop on MEMS : March 2016
  • Four day workshop on robotics: : January 2017
  • Five day workshop on robotics and IoT : June 2018
  • Five Days FDP on Robotics and IoT : July 2018
  • Embedded System Design Based on Arduino Board: March 2019

Pursuing PhD in VLSI Architectures from Indian Institute of information Technology [IIIT], Kottayam.