Dr. S. Krishna Kumar received his PhD in Digital VLSI Testing from the Indian Institute of Technology, Kharagpur and Post-graduation in Computer Science from the Indian Institute of Technology, Madras. He has over 25 years of experience. He served Amrita Vishwa Vidyapeetham, Coimbatore for 16 years. Since July 2013, he is a professor at the Federal Institute of Science & Technology.
1. Resource person for workshop on Digital Front End Design as part of Agnitio on 02/06/2022
2. Resource person for workshop on Workshop on Concept to Semicustom Design as part of Agnitio on 02/06/2022
3. Technical Talk on Introduction to MOSFET for S4 ECE on 14/07/2022
4. Participated in the 3 days TEQIP-II sponsored SDP on “Advanced Micro/Nanosensor Technologies” at Govt Engg college, Palakkad from 18/07/2022 to 20/07/2022
5. External examiner for MTech Thesis evaluation at Rajagiri School of Engineering, Kakkanad on 25/07/2022
6. Attended TEQIP-II Sponsored Online Faculty Development Programme on Environmental Issues in Societal Development organized by the Department of Civil Engineering, College of Engineering Kidangoor, Kottayam, Kerala, from 22/08/2022 to 28/08/2022
7. Attended FDP on Advanced Research and Quality Publications conducted by Department of MCA, FISAT from 29/08/2022 to 02/09/2022
• Customizing Completely Specified Pattern Set Targeting Dynamic and Leakage Power Reduction During Testing by S. Krishna Kumar, Subhadip Kundu, Santanu Chattopadhyay Integration, the VLSI Journal, Volume 45, Issue 2, March 2012, Pages 211–221.
• Particle Swarm Optimization Based Scheme for Low Power March Sequence Generation for Memory Testing by S. Krishna Kumar, S. Kaundinya, Santanu Chattopadhyay Asian Test Symposium, ATS 2010, Shanghai, China, pp.401- 406 (2010).
• Particle Swarm Optimization based Vector Reordering for Low Power Testing by S. Krishna Kumar, S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay The Sec. Int. Conf. on Computing, Communication and Networking Technologies, ICCCNT 2010, Karur, India, pp.1-5 (2010).
• Customizing Pattern Set for Test Power Reduction via Improved X-identification and Reordering by S. Krishna Kumar, S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay 16th International Symposium on Low Power Electronics and Design 2010, ISLPD 2010, Austin, Texas, USA, pp.177-182 (2010).
• Test Power Reduction with Test-Time Trade-Off by Subhadip Kundu, S. Krishna Kumar, Santanu Chattopadhyay IEEE International Symposium on Circuits and Systems, ISCAS 2010, Paris, (2010).
• Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption by Subhadip Kundu, S. Krishna Kumar, Santanu Chattopadhyay Asian Test Symposium, ATS 2009, Taiwan, pp.307-312 (2009).
• Circuit Partitioning Using Particle Swarm Optimization for Pseudo- Exhaustive Testing by S. Krishna Kumar, P. Uday Bhaskar, Santanu Chattopadhyay, Pradip Mandal International Conference on Advances in Recent Technologies in Communication and Computing, ARTCom 2009, Kottayam, India, pp.346- 350 (2009).
• Low Power Pseudoexhaustive Testing with Cellular Automata by S. Krishna Kumar, P. Uday Bhaskar, Santanu Chattopadhyay International Conference on Advances in Computing, Control, and Telecommunication Technologies, ACT 2009, Trivandrum, India, pp.419-423 (2009).